/** @file
Phytium parameter table define.
There are different parameter table versions for different chips:
1.PLL
V1 : Pd2008/Ps2364
V2 : Pe2204
2.PCIE
V1 : Pd2008
V2 : Pe2204
V3 : Ps2364
3.DDR
V1 : Pd2008
V2 : Pe2204
V3 : Ps2364
4.COMMON
V1 : Pd2008/Pe2204
V2 : Ps2364

Copyright (C) 2022 - 2023, Phytium Technology Co., Ltd. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

**/

#ifndef PHYTIUM_PARAMETER_H_
#define PHYTIUM_PARAMETER_H_

#include <Library/BaseMemoryLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>

#include <Uefi/UefiBaseType.h>

#define O_PARAMETER_BASE            (FixedPcdGet64 (PcdParameterTableBase))

#define PM_PLL_OFFSET               (FixedPcdGet64 (PcdParameterPllOffset))
#define PM_COMMON_OFFSET            (FixedPcdGet64 (PcdParameterCommonOffset))
#define PM_DDR_OFFSET               (FixedPcdGet64 (PcdParameterDdrOffset))
#define PM_BOARD_OFFSET             (FixedPcdGet64 (PcdParameterBoardOffset))
#define PM_SECURE_OFFSET            (FixedPcdGet64 (PcdParameterSecureOffset))
#define PM_PCIE_OFFSET              (FixedPcdGet64 (PcdParameterPcieOffset))
#define PM_C2C_OFFSET               (FixedPcdGet64 (PcdParameterC2COffset))
#define PM_PCIE_OFFSET_DIE_V3       0x100

//PLL Pd2008/Ps2364
#define PARAMETER_PLL_MAGIC_V1              0x54460010
//PLL Pe2204
#define PARAMETER_PLL_MAGIC_V2              0x54460020
//PCIE Pd2008
#define PARAMETER_PCIE_MAGIC_V1             0x54460011
//PCIE Pe2204
#define PARAMETER_PCIE_MAGIC_V2             0x54460021
//PCIE Ps2364
#define PARAMETER_PCIE_MAGIC_V3             0x54460031
//COMMON Pd2008/Pe2204
#define PARAMETER_COMMON_MAGIC_V1           0x54460013
//COMMON Ps2364
#define PARAMETER_COMMON_MAGIC_V2           0x54460023
//DDR Pd2008
#define PARAMETER_DDR_MAGIC_V1              0x54460014
//DDR Pe2204
#define PARAMETER_DDR_MAGIC_V2              0x54460024
//DDR Ps2364
#define PARAMETER_DDR_MAGIC_V3              0x54460034
//BOARD
#define PARAMETER_BOARD_MAGIC               0x54460015
//BOARD Ps2364
#define PARAMETER_BOARD_MAGIC_V2            0x5446001b
//C2C Ps2364
#define PARAMETER_C2C_MAGIC                 0x54460015

#define PM_PLL_V1           0
#define PM_PLL_V2           1
#define PM_PCIE_V1          2
#define PM_PCIE_V2          3
#define PM_PCIE_V3          4
#define PM_COMMON_V1        5
#define PM_DDR_V1           6
#define PM_DDR_V2           7
#define PM_DDR_V3           8
#define PM_BOARD            9
#define PM_SECURE           10
#define PM_COMMON_V2        11
#define PM_C2C              12
#define PM_BOARD_V2         13

//
//PCIE V1 DEFINES
//
//Mode
#define  PCIE_V1_RC_MODE                      0
#define  PCIE_V1_EP_MODE                      1

//split
#define  PCIE_V1_SPLIT_NO_INIT                0
#define  PCIE_V1_SPLIT_X8X8                   1
#define  PCIE_V1_SPLIT_X16                    3

//Base Config
#define  PCIE_V1_SPEED_AUTO                   0
#define  PCIE_V1_SPEED_GEN1                   1
#define  PCIE_V1_SPEED_GEN2                   2
#define  PCIE_V1_SPEED_GEN3                   3

#define  PCIE_V1_CONTROLLER_ENABLE            0
#define  PCIE_V1_CONTROLLER_CLOSE             1

//
//PCIE V2 DEFINES
//
//split
#define  PCIE_V2_SPLIT_PEU_NO_INIT            0
#define  PCIE_V2_SPLIT_PEU_X4                 1
#define  PCIE_V2_SPLIT_PEU_X2X1X1             3
#define  PCIE_V2_SPLIT_PEU_X1X1X1X1           5

#define  PCIE_V2_SPLIT_PSU_NO_INIT            0
#define  PCIE_V2_SPLIT_PSU_X1X1               1
#define  PCIE_V2_SPLIT_PSU_X0X1               3
#define  PCIE_V2_SPLIT_PSU_X1X0               5

//mode
#define  PCIE_V2_RC_MODE                      1
#define  PCIE_V2_EP_MODE                      0

//Port Enable
#define  PCIE_V2_CONTROLLER_ENABLE            0
#define  PCIE_V2_CONTROLLER_CLOSE             1

//Speed
#define  PCIE_V2_SPEED_AUTO                   0
#define  PCIE_V2_SPEED_GEN1                   1
#define  PCIE_V2_SPEED_GEN2                   2
#define  PCIE_V2_SPEED_GEN3                   3

//
//PCIE V3 DEFINES
//
//Split
#define  PCIE_V3_PCIE0_SPLIT_X16              0
#define  PCIE_V3_PCIE0_SPLIT_X8X8             1
#define  PCIE_V3_PCIE0_SPLIT_X8X4X4           3
#define  PCIE_V3_PCIE0_SPLIT_X4X4X4X4         4

#define  PCIE_V3_PCIE1_SPLIT_X1X1X1X1         0

#define  PCIE_V3_PCIE23_SPLIT_X8X8_PCIE       0
#define  PCIE_V3_PCIE23_SPLIT_X8X8_PCIE_C2C   4
#define  PCIE_V3_PCIE23_SPLIT_X8X8_C2C_PCIE   5
#define  PCIE_V3_PCIE23_SPLIT_X8X8_C2C        6

//Speed
#define  PCIE_V3_SPEED_GEN1                   0
#define  PCIE_V3_SPEED_GEN2                   1
#define  PCIE_V3_SPEED_GEN3                   2
#define  PCIE_V3_SPEED_GEN4                   3
#define  PCIE_V3_SPEED_GEN5                   4

//
//DDR V1 DEFINES
//
//cpu odt
#define  DDR_V1_CPU_ODT_34OHM                 0x0
#define  DDR_V1_CPU_ODT_40OHM                 0x1
#define  DDR_V1_CPU_ODT_48OHM                 0x2
#define  DDR_V1_CPU_ODT_60OHM                 0x3
#define  DDR_V1_CPU_ODT_80OHM                 0x4
#define  DDR_V1_CPU_ODT_120OHM                0x5
#define  DDR_V1_CPU_ODT_240OHM                0x6
#define  DDR_V1_CPU_ODT_HIZ                   0x7

//cpu driver
#define  DDR_V1_CPU_DRV_34OHM                 0x0
#define  DDR_V1_CPU_DRV_40OHM                 0x1
#define  DDR_V1_CPU_DRV_48OHM                 0x2
#define  DDR_V1_CPU_DRV_60OHM                 0x3
#define  DDR_V1_CPU_DRV_80OHM                 0x4
#define  DDR_V1_CPU_DRV_120OHM                0x5
#define  DDR_V1_CPU_DRV_240OHM                0x6
#define  DDR_V1_CPU_DRV_HIZ                   0x7

//dimm driver
#define  DDR_V1_MR_DRV_34OHM                  0x0
#define  DDR_V1_MR_DRV_48OHM                  0x1

//dimm rtt_nom
#define  DDR_V1_RTT_NOM_34OHM                 0x0
#define  DDR_V1_RTT_NOM_40OHM                 0x1
#define  DDR_V1_RTT_NOM_48OHM                 0x2
#define  DDR_V1_RTT_NOM_60OHM                 0x3
#define  DDR_V1_RTT_NOM_80OHM                 0x4
#define  DDR_V1_RTT_NOM_120OHM                0x5
#define  DDR_V1_RTT_NOM_240OHM                0x6
#define  DDR_V1_RTT_NOM_DISABLE               0x7

//dimm rtt_park
#define  DDR_V1_RTT_PARK_40OHM                0x0
#define  DDR_V1_RTT_PARK_48OHM                0x1
#define  DDR_V1_RTT_PARK_60OHM                0x2
#define  DDR_V1_RTT_PARK_80OHM                0x3
#define  DDR_V1_RTT_PARK_120OHM               0x4
#define  DDR_V1_RTT_PARK_2400OHM              0x5
#define  DDR_V1_RTT_PARK_DISABLE              0x6

//dimm rtt_wr
#define  DDR_V1_RTT_WR_DISABLE                0x0
#define  DDR_V1_RTT_WR_120OHM                 0x1
#define  DDR_V1_RTT_WR_240HM                  0x2
#define  DDR_V1_RTT_WR_HIZ                    0x3

//dimm type
#define  DDR_V1_DIMM_TYPE_RDIMM               1
#define  DDR_V1_DIMM_TYPE_UDIMM               2
#define  DDR_V1_DIMM_TYPE_SODIMM              3
#define  DDR_V1_DIMM_TYPE_LRDIMM              4

//data width
#define  DDR_V1_DATA_WIDTH_X4                 0
#define  DDR_V1_DATA_WIDTH_X8                 1
#define  DDR_V1_DATA_WIDTH_X16                2
#define  DDR_V1_DATA_WIDTH_X32                3

//mirro type
#define  DDR_V1_MIRROR_TYPE_STARDARD          0
#define  DDR_V1_MIRROR_TYPE_MIRROR            1

//rank num
#define  DDR_V1_RANK_NUM_1                    1
#define  DDR_V1_RANK_NUM_2                    2
#define  DDR_V1_RANK_NUM_4                    4

//
//DDR V2 DEFINES
//
//DQ OE Timing
#define  DDR_V2_DQ_OE_TIMING_42               0
#define  DDR_V2_DQ_OE_TIMING_51               1
#define  DDR_V2_DQ_OE_TIMING_53               2

//Hafl Bit Width
#define  DDR_V2_BIT_WIDTH_32BIT               1
#define  DDR_V2_BIT_WIDTH_64BIT               0

//cpu odt ddr4
#define  DDR_V2_DDR4_CPU_ODT_34OHM            0x0
#define  DDR_V2_DDR4_CPU_ODT_40OHM            0x1
#define  DDR_V2_DDR4_CPU_ODT_48OHM            0x2
#define  DDR_V2_DDR4_CPU_ODT_60OHM            0x3
#define  DDR_V2_DDR4_CPU_ODT_80OHM            0x4
#define  DDR_V2_DDR4_CPU_ODT_120OHM           0x5
#define  DDR_V2_DDR4_CPU_ODT_240OHM           0x6
#define  DDR_V2_DDR4_CPU_ODT_HIZ              0x7

//dq_odt lpddr4
#define  DDR_V2_LPDDR4_DQ_ODT_DISABLE         0x0
#define  DDR_V2_LPDDR4_DQ_ODT_240OHM          0x1
#define  DDR_V2_LPDDR4_DQ_ODT_120OHM          0x2
#define  DDR_V2_LPDDR4_DQ_ODT_80OHM           0x3
#define  DDR_V2_LPDDR4_DQ_ODT_60OHM           0x4
#define  DDR_V2_LPDDR4_DQ_ODT_48OHM           0x5
#define  DDR_V2_LPDDR4_DQ_ODT_40OHM           0x6

//cpu driver ddr4
#define  DDR_V2_CPU_DRV_34OHM                 0x0
#define  DDR_V2_CPU_DRV_40OHM                 0x1
#define  DDR_V2_CPU_DRV_48OHM                 0x2
#define  DDR_V2_CPU_DRV_60OHM                 0x3
#define  DDR_V2_CPU_DRV_80OHM                 0x4
#define  DDR_V2_CPU_DRV_120OHM                0x5
#define  DDR_V2_CPU_DRV_240OHM                0x6
#define  DDR_V2_CPU_DRV_HIZ                   0x7

//ca odt lpddr4
#define  DDR_V2_CA_ODT_DISABLE                0x0
#define  DDR_V2_CA_ODT_240OHM                 0x1
#define  DDR_V2_CA_ODT_120OHM                 0x2
#define  DDR_V2_CA_ODT_80OHM                  0x3
#define  DDR_V2_CA_ODT_60OHM                  0x4
#define  DDR_V2_CA_ODT_48OHM                  0x5
#define  DDR_V2_CA_ODT_40OHM                  0x6

//dimm driver
#define  DDR_V2_MR_DRV_34OHM                  0x0
#define  DDR_V2_MR_DRV_48OHM                  0x1

//dimm rtt_nom
#define  DDR_V2_RTT_NOM_34OHM                 0x0
#define  DDR_V2_RTT_NOM_40OHM                 0x1
#define  DDR_V2_RTT_NOM_48OHM                 0x2
#define  DDR_V2_RTT_NOM_60OHM                 0x3
#define  DDR_V2_RTT_NOM_80OHM                 0x4
#define  DDR_V2_RTT_NOM_120OHM                0x5
#define  DDR_V2_RTT_NOM_240OHM                0x6
#define  DDR_V2_RTT_NOM_DISABLE               0x7

//dimm rtt_park
#define  DDR_V2_RTT_PARK_40OHM                0x0
#define  DDR_V2_RTT_PARK_48OHM                0x1
#define  DDR_V2_RTT_PARK_60OHM                0x2
#define  DDR_V2_RTT_PARK_80OHM                0x3
#define  DDR_V2_RTT_PARK_120OHM               0x4
#define  DDR_V2_RTT_PARK_2400OHM              0x5
#define  DDR_V2_RTT_PARK_DISABLE              0x6

//dimm rtt_wr
#define  DDR_V2_RTT_WR_DISABLE                0x0
#define  DDR_V2_RTT_WR_120OHM                 0x1
#define  DDR_V2_RTT_WR_240HM                  0x2
#define  DDR_V2_RTT_WR_HIZ                    0x3

//dimm type
#define  DDR_V2_DIMM_TYPE_RDIMM               1
#define  DDR_V2_DIMM_TYPE_UDIMM               2
#define  DDR_V2_DIMM_TYPE_SODIMM              3
#define  DDR_V2_DIMM_TYPE_LRDIMM              4

//data width
#define  DDR_V2_DATA_WIDTH_X4                 0
#define  DDR_V2_DATA_WIDTH_X8                 1
#define  DDR_V2_DATA_WIDTH_X16                2
#define  DDR_V2_DATA_WIDTH_X32                3

//mirro type
#define  DDR_V2_MIRROR_TYPE_STARDARD          0
#define  DDR_V2_MIRROR_TYPE_MIRROR            1

//rank num
#define  DDR_V2_RANK_NUM_1                    1
#define  DDR_V2_RANK_NUM_2                    2
#define  DDR_V2_RANK_NUM_4                    4

//dram type
#define  DDR_V2_DRAM_TYPE_DDR4                0xC
#define  DDR_V2_DRAM_TYPE_LPDDR4              0x10
#define  DDR_V2_DRAM_TYPE_DDR5                0x12

//
//DDR V3 DEFINES
//
//Refresh mode
#define  DDR_V3_REFRESH_MODE_1X               0
#define  DDR_V3_REFRESH_MODE_2X               1
#define  DDR_V3_REFRESH_MODE_4X               2

//Temperature refresh mode
#define  DDR_V3_TEMP_REFRESH_NORMAL           0
#define  DDR_V3_TEMP_REFRESH_NORMAL_TEMP      0
#define  DDR_V3_TEMP_REFRESH_NORMAL_EXTENDED  0

//special training dram type
#define  DDR_V3_SPEC_DRAM_TYPE_DDR4           0xC
#define  DDR_V3_SPEC_DRAM_TYPE_LPDDR4         0x10
#define  DDR_V3_SPEC_DRAM_TYPE_DDR5           0x12

//cpu odt ddr4
#define  DDR_V3_DDR4_CPU_ODT_34OHM            0x0
#define  DDR_V3_DDR4_CPU_ODT_40OHM            0x1
#define  DDR_V3_DDR4_CPU_ODT_48OHM            0x2
#define  DDR_V3_DDR4_CPU_ODT_60OHM            0x3
#define  DDR_V3_DDR4_CPU_ODT_80OHM            0x4
#define  DDR_V3_DDR4_CPU_ODT_120OHM           0x5
#define  DDR_V3_DDR4_CPU_ODT_240OHM           0x6
#define  DDR_V3_DDR4_CPU_ODT_HIZ              0x7

//dq_odt lpddr4
#define  DDR_V3_LPDDR4_DQ_ODT_DISABLE         0x0
#define  DDR_V3_LPDDR4_DQ_ODT_240OHM          0x1
#define  DDR_V3_LPDDR4_DQ_ODT_120OHM          0x2
#define  DDR_V3_LPDDR4_DQ_ODT_80OHM           0x3
#define  DDR_V3_LPDDR4_DQ_ODT_60OHM           0x4
#define  DDR_V3_LPDDR4_DQ_ODT_48OHM           0x5
#define  DDR_V3_LPDDR4_DQ_ODT_40OHM           0x6

//cpu driver ddr4
#define  DDR_V3_CPU_DRV_34OHM                 0x0
#define  DDR_V3_CPU_DRV_40OHM                 0x1
#define  DDR_V3_CPU_DRV_48OHM                 0x2
#define  DDR_V3_CPU_DRV_60OHM                 0x3
#define  DDR_V3_CPU_DRV_80OHM                 0x4
#define  DDR_V3_CPU_DRV_120OHM                0x5
#define  DDR_V3_CPU_DRV_240OHM                0x6
#define  DDR_V3_CPU_DRV_HIZ                   0x7

//ca odt lpddr4
#define  DDR_V3_CA_ODT_DISABLE                0x0
#define  DDR_V3_CA_ODT_240OHM                 0x1
#define  DDR_V3_CA_ODT_120OHM                 0x2
#define  DDR_V3_CA_ODT_80OHM                  0x3
#define  DDR_V3_CA_ODT_60OHM                  0x4
#define  DDR_V3_CA_ODT_48OHM                  0x5
#define  DDR_V3_CA_ODT_40OHM                  0x6

//dimm driver
#define  DDR_V3_MR_DRV_34OHM                  0x0
#define  DDR_V3_MR_DRV_48OHM                  0x1

//dimm rtt_nom
#define  DDR_V3_RTT_NOM_34OHM                 0x0
#define  DDR_V3_RTT_NOM_40OHM                 0x1
#define  DDR_V3_RTT_NOM_48OHM                 0x2
#define  DDR_V3_RTT_NOM_60OHM                 0x3
#define  DDR_V3_RTT_NOM_80OHM                 0x4
#define  DDR_V3_RTT_NOM_120OHM                0x5
#define  DDR_V3_RTT_NOM_240OHM                0x6
#define  DDR_V3_RTT_NOM_DISABLE               0x7

//dimm rtt_park
#define  DDR_V3_RTT_PARK_40OHM                0x0
#define  DDR_V3_RTT_PARK_48OHM                0x1
#define  DDR_V3_RTT_PARK_60OHM                0x2
#define  DDR_V3_RTT_PARK_80OHM                0x3
#define  DDR_V3_RTT_PARK_120OHM               0x4
#define  DDR_V3_RTT_PARK_2400OHM              0x5
#define  DDR_V3_RTT_PARK_DISABLE              0x6

//dimm rtt_wr
#define  DDR_V3_RTT_WR_DISABLE                0x0
#define  DDR_V3_RTT_WR_120OHM                 0x1
#define  DDR_V3_RTT_WR_240HM                  0x2
#define  DDR_V3_RTT_WR_HIZ                    0x3

//dimm type
#define  DDR_V3_DIMM_TYPE_RDIMM               1
#define  DDR_V3_DIMM_TYPE_UDIMM               2
#define  DDR_V3_DIMM_TYPE_SODIMM              3
#define  DDR_V3_DIMM_TYPE_LRDIMM              4

//data width
#define  DDR_V3_DATA_WIDTH_X4                 0
#define  DDR_V3_DATA_WIDTH_X8                 1
#define  DDR_V3_DATA_WIDTH_X16                2
#define  DDR_V3_DATA_WIDTH_X32                3

//mirro type
#define  DDR_V3_MIRROR_TYPE_STARDARD          0
#define  DDR_V3_MIRROR_TYPE_MIRROR            1

//rank num
#define  DDR_V3_RANK_NUM_1                    1
#define  DDR_V3_RANK_NUM_2                    2
#define  DDR_V3_RANK_NUM_4                    4

//dram type
#define  DDR_V3_DRAM_TYPE_DDR4                0xC
#define  DDR_V3_DRAM_TYPE_LPDDR4              0x10
#define  DDR_V3_DRAM_TYPE_DDR5                0x12

//mucconfig1
#define  DDR_V3_MCU_BASE_CONFIG_V3_1_I2C      0x1
#define  DDR_V3_MCU_BASE_CONFIG_V3_1_I3C      0x0
#define  DDR_V3_MCU_BASE_CONFIG_V3_1_DDR4     0x1
#define  DDR_V3_MCU_BASE_CONFIG_V3_1_DDR5     0x0

#pragma pack(1)

typedef struct _PARAMETER_HEADER {
  UINT32  Magic;
  UINT32  Version;
  UINT32  Size;
  UINT8   DieID;          //Multi-die chip is valid, other chips are reserved
  UINT8   Reserved[3];
} PARAMETER_HEADER;

//
//PLL Paramater V1 Pd2008/Ps2364
//
typedef struct _PARAMETER_PLL_CONFIG_V1 {
  PARAMETER_HEADER    Head;
  UINT32              CoreFreq;
  UINT32              Reserved1;
  UINT32              LmuFreq;
  UINT32              Reserved2[4];
} PARAMETER_PLL_CONFIG_V1;

//
//PLL Parameter V2 Pe2204
//
typedef struct _PARAMETER_PLL_CONFIG_V2 {
  PARAMETER_HEADER    Head;
  UINT32              PerformanceCoreFreq;
  UINT32              Reserved1;
  UINT32              EfficiencyCoreFreq;
  UINT32              Reserved2;
  UINT32              LmuFreq;
  UINT32              Reserved3[4];
} PARAMETER_PLL_CONFIG_V2;

//
//PCIE Controller Equal Value
//
typedef union  _PCIE_CONTROLLER_EQUAL_VALUE {
  struct  {
    UINT32    Value      :  9;
    UINT32    Reserved   :  23;
  } Bits;
  UINT32  Uint32;
} PCIE_CONTROLLER_EQUAL_VALUE;

//
//PCIE Config Parameter V1 Pd2008
//
//
//PCIE Controller Base Config V1
//
typedef union _PCIE_CONTROLLER_BASE_CONFIG_V1 {
  struct  {
    UINT32    Speed      :  9;
    UINT32    Enable     :  1;
    UINT32    Reserved0  : 22;
  } Bits;
  UINT32  Uint32;
} PCIE_CONTROLLER_BASE_CONFIG_V1;

//
//PCIE Controller Config V1
//
typedef struct _PCIE_CONTROLLER_CONFIG_V1 {
  PCIE_CONTROLLER_BASE_CONFIG_V1  BaseConfig[3];
  PCIE_CONTROLLER_EQUAL_VALUE     EqualValue[3];
} PCIE_CONTROLLER_CONFIG_V1;

//
//PCIE function config V1
//
typedef union _PCIE_FUNCTION_CONFIG_V1 {
  struct {
    UINT32    Pcie0Split    :  4;
    UINT32    Pcie0Mode     :  2;
    UINT32    Reserved1     : 10;
    UINT32    Pcie1Split    :  4;
    UINT32    Pcie1Mode     :  2;
    UINT32    Reserved2     : 10;
  } Bits;
  UINT32    Uint32;
} PCIE_FUNCTION_CONFIG_V1;

//
//PCIE Parameter V1
//
typedef struct _PARAMETER_PCIE_CONFIG_V1 {
  PARAMETER_HEADER                Head;
  UINT32                          Reserved0;
  PCIE_FUNCTION_CONFIG_V1         Function;
  UINT32                          Reserved3[4];
  PCIE_CONTROLLER_CONFIG_V1       Pcie0Config;
  UINT32                          Reserved4[20];
  PCIE_CONTROLLER_CONFIG_V1       Pcie1Config;
} PARAMETER_PCIE_CONFIG_V1;

//
//PCIE Config Parameter V2 Pe2204
//
//
//PCIE function config V2
//
typedef union _PCIE_FUNCTION_CONFIG_V2 {
  struct {
    UINT32    Pcie0Split    :  4;
    UINT32    Reserved0     :  12;
    UINT32    Pcie1Split    :  4;
    UINT32    Reserved1     :  12;
  } Bits;
  UINT32    Uint32;
} PCIE_FUNCTION_CONFIG_V2;

//
//PCIE 0 Controller  Config V2
//
typedef union _PCIE_0_CONTROLLER_BASE_CONFIG_V2 {
  struct {
    UINT32    Speed     :9;
    UINT32    Close     :1;
    UINT32    Reserved0 :6;
    UINT32    Mode      :1;
    UINT32    Reserved1 :15;
  } Bits;
  UINT32    Uint32;
} PCIE_0_CONTROLLER_BASE_CONFIG_V2;

//
//PCIE 1 Controller  Config V2
//
typedef union _PCIE_1_CONTROLLER_BASE_CONFIG_V2 {
  struct {
    UINT32    Speed     :  9;
    UINT32    Close     :  1;
    UINT32    Reserved0 : 22;
  } Bits;
  UINT32    Uint32;
} PCIE_1_CONTROLLER_BASE_CONFIG_V2;

//
//PCIE Parameter V2
//
typedef struct _PARAMETER_PCIE_CONFIG_V2 {
  PARAMETER_HEADER                  Head;
  UINT32                            Reserved0;
  PCIE_FUNCTION_CONFIG_V2           Function;
  UINT32                            Reserved1[4];
  PCIE_0_CONTROLLER_BASE_CONFIG_V2  Pcie0Config[2];
  UINT32                            Reserved2[2];
  PCIE_CONTROLLER_EQUAL_VALUE       Pcie0EqualValue[2];
  UINT32                            Revserved3[20];
  PCIE_1_CONTROLLER_BASE_CONFIG_V2  Pcie1Config[4];
  PCIE_CONTROLLER_EQUAL_VALUE       Pcie1EqualValue[4];
} PARAMETER_PCIE_CONFIG_V2;

//
//PCIE Config Parameter V3 Ps2364
//
//
//PCIE Split mode V3
//
typedef union _PCIE_SPILT_MODE_V3 {
  struct {
    UINT32    Mode0    :   4;
    UINT32    Mode1    :   4;
    UINT32    Mode2    :   4;
    UINT32    Mode3    :   4;
    UINT32    Reserved :  16;
  } Bits;
  UINT32    Uint32;
} PCIE_SPILT_MODE_V3;

//
//Advanced function
//
typedef union _PCIE_ADVANCED_FUNCTION {
  struct {
    UINT32    HotPlug      :   1;
    UINT32    Aer          :   1;
    UINT32    Ari          :   1;
    UINT32    Aspm         :   1;
    UINT32    Reserved     :  28;
  } Bits;
  UINT32    Uint32;
} PCIE_ADVANCED_FUNCTION;

//
//PCIE Controller  Enable
//
typedef union _PCIE_CONTROLLER_ENABLE_V3 {
  struct  {
    UINT32    C0Close       :    1;
    UINT32    C1Close       :    1;
    UINT32    C2Close       :    1;
    UINT32    C3Close       :    1;
    UINT32    C4Close       :    1;
    UINT32    C5Close       :    1;
    UINT32    C6Close       :    1;
    UINT32    C7Close       :    1;
    UINT32    C8Close       :    1;
    UINT32    C9Close       :    1;
    UINT32    C10Close      :    1;
    UINT32    C11Close      :    1;
    UINT32    Reserved      :   20;
  } Bits;
  UINT32    Uint32;
} PCIE_CONTROLLER_ENABLE_V3;

//
//PCIE RAS Config V3
//
typedef struct _PCIE_RAS_CONFIG_V3 {
  union {
    struct {
      UINT16    Enable        :    1;
      UINT16    Reserved      :   15;
    } Bits;
    UINT16    Uint16;
  } RasEnable;
  UINT16    Value;
} PCIE_RAS_CONFIG_V3;

//
//PCIE  Speed Config V3
//
typedef union _PCIE_SPEED_CONFIG_V3 {
  struct {
    UINT64    C0Speed    :   3;
    UINT64    C1Speed    :   3;
    UINT64    C2Speed    :   3;
    UINT64    C3Speed    :   3;
    UINT64    C4Speed    :   3;
    UINT64    C5Speed    :   3;
    UINT64    C6Speed    :   3;
    UINT64    C7Speed    :   3;
    UINT64    C8Speed    :   3;
    UINT64    C9Speed    :   3;
    UINT64    C10Speed   :   3;
    UINT64    C11Speed   :   3;
    UINT64    Reserved   :  28;
  } Bits;
  UINT64    Uint64;
} PCIE_SPEED_CONFIG_V3;

//
//PCIE Parameter V3 Ps2364
//
typedef struct _PARAMETER_PCIE_CONFIG_V3 {
  PARAMETER_HEADER                  Head;
  PCIE_SPILT_MODE_V3                Split;
  PCIE_ADVANCED_FUNCTION            Advanced;
  PCIE_RAS_CONFIG_V3                RasConfig;
  PCIE_CONTROLLER_ENABLE_V3         Enable;
  PCIE_SPEED_CONFIG_V3              Speed;
  UINT32                            EqualValue[12];
  UINT16                            PhysicalSlotNum[12];
} PARAMETER_PCIE_CONFIG_V3;

//
//Commom Parameter V1
//
typedef struct _PARAMETER_COMMON_CONFIG_V1 {
  PARAMETER_HEADER                  Head;
  UINT64                            CoreBitMap;
  UINT32                            Misc1;
} PARAMETER_COMMON_CONFIG_V1;

//
//Commom Parameter V1
//
typedef struct _PARAMETER_COMMON_CONFIG_V2 {
  PARAMETER_HEADER                  Head;
  UINT64                            CoreBitMap[8];  //8die
  UINT32                            Misc1;
} PARAMETER_COMMON_CONFIG_V2;

//
//DDR Config Parameter V1 Pd2008
//
//
//DDR Training Debug
//
typedef union _DDR_TRAINING_DEBUG {
  struct {
    UINT8     Reversed        :    1;
    UINT8     Delay           :    1;
    UINT8     Detailed        :    1;
    UINT8     Register        :    1;
    UINT8     Error           :    1;
    UINT8     REserved1       :    3;
  } Bits;
  UINT8    Uint8;
} DDR_TRAINING_DEBUG;

//
//DDR Data Byte Swap
//
typedef union _DDR_BYTE_SWAP {
  struct {
    UINT32     DimmType0       :    4;
    UINT32     DimmType1       :    4;
    UINT32     DimmType2       :    4;
    UINT32     DimmType3       :    4;
    UINT32     DimmType4       :    4;
    UINT32     DimmType5       :    4;
    UINT32     DimmType6       :    4;
    UINT32     DimmType7       :    4;
  } Bits;
  UINT32    Uint32;
} DDR_BYTE_SWAP;

//
//DDR slice dq swizzle
//
typedef union _DDR_SLICE_DQ_SWIZZLE {
  struct {
    UINT32     Dq0             :    4;
    UINT32     Dq1             :    4;
    UINT32     Dq2             :    4;
    UINT32     Dq3             :    4;
    UINT32     Dq4             :    4;
    UINT32     Dq5             :    4;
    UINT32     Dq6             :    4;
    UINT32     Dq7             :    4;
  } Bits;
  UINT32    Uint32;
} DDR_SLICE_DQ_SWIZZLE;

//
// DDr Channel Enable V1
//
typedef union _DDR_CHANNEL_CONTROL_V1 {
  struct {
    UINT8      Ch0          :   1;
    UINT8      Ch1          :   1;
    UINT8      Reserved     :   6;
  } Bits;
  UINT8    Uint8;
} DDR_CHANNEL_CONTROL_V1;

//
// DDR Base Config V1
//
typedef union _DDR_BASE_CONFIG_V1 {
  struct {
    UINT32    Ecc                     :    1;
    UINT32    SpdForce                :    1;
    UINT32    DqOeTiming2             :    1;
    UINT32    MultiRankPerformance    :    1;
    UINT32    DoubleRankStable        :    1;
    UINT32    X2Refresh               :    1;
    UINT32    LowPower                :    1;
    UINT32    Reserved0               :    1;
    UINT32    DmEnable                :    1;
    UINT32    Reserved1               :    16;
    UINT32    Preamble2TPlus          :    1;
    UINT32    PdaInvert               :    1;
    UINT32    DqOeTiming1             :    1;
    UINT32    OneTwo                  :    1;
    UINT32    Performance             :    1;
    UINT32    T2Preamble              :    1;
    UINT32    SkipScrub               :    1;
  } Bits;
  UINT32    Uint32;
} DDR_BASE_CONFIG_V1;

//
// DDR Training parameter set V1
//
typedef union _DDR_TRAIN_PARAM_V1 {
  struct {
    UINT32    CpuOdt            :    4;
    UINT32    CpuDrv            :    4;
    UINT32    MrDrv             :    4;
    UINT32    RttNom            :    4;
    UINT32    RttPark           :    4;
    UINT32    RttWr             :    4;
    UINT32    Reversed          :    8;
  } Bits;
  UINT32    Uint32;
} DDR_TRAIN_PARAM_V1;

//
//DDR Channel information V1
//
typedef struct _DDR_CHANNEL_INFOR_V1 {
  UINT8    DimmType;
  UINT8    DataWidth;
  UINT8    MirrorType;
  UINT8    EccType;
  UINT8    Reserved0;
  UINT8    RankNum;
  UINT8    RowNum;
  UINT8    ColumnNum;
  UINT8    BankGroupNum;
  UINT8    BankNum;
  UINT16   ModuleManId;
  UINT16   TAAmin;
  UINT16   TRCDmin;
  UINT16   TRPmin;
  UINT16   TRASmin;
  UINT16   TRCmin;
  UINT16   TFAWmin;
  UINT16   TRRDSmin;
  UINT16   TRRDLmin;
  UINT16   TCCDLmin;
  UINT16   TWRmin;
  UINT16   TWTRSmin;
  UINT16   TWTRLmin;
  UINT8    Reserved1[28];
} DDR_CHANNEL_INFOR_V1;
//
// DDR Parameter V1
//
typedef struct _PARAMETER_DDR_CONFIG_V1 {
  PARAMETER_HEADER                  Head;
  DDR_CHANNEL_CONTROL_V1            ChEnable;
  DDR_BASE_CONFIG_V1                BaseConfig;
  DDR_TRAINING_DEBUG                Debug;
  UINT8                             Recover;
  DDR_TRAIN_PARAM_V1                Param;
  UINT8                             Reverved0[5];
  DDR_CHANNEL_INFOR_V1              ChannelInfo[2];
} PARAMETER_DDR_CONFIG_V1;

//
//DDR Config Parameter V2 Pe2204
//
//
// DDR Mcu Base Config V2
//
typedef union _DDR_MCU_BASE_CONFIG_V2 {
  struct {
    UINT64    SpdForce        :    1;
    UINT64    EccEnable       :    1;
    UINT64    DmEnable        :    1;
    UINT64    Performance     :    1;
    UINT64    T2Preamble      :    1;
    UINT64    OneTwo          :    1;
    UINT64    SkipMemClean    :    1;
    UINT64    PdaInvert       :    1;
    UINT64    DqOeTiming      :    2;
    UINT64    MultiRankHigh   :    1;
    UINT64    X2Fresh         :    1;
    UINT64    AutoLowPower    :    1;
    UINT64    HalfBitWidth    :    1;
    UINT64    Dbi             :    1;
    UINT64    Reserved        :   49;
  } Bits;
  UINT64    Uint64;
} DDR_MCU_BASE_CONFIG_V2;

//
//All channel ddr information V2
//
typedef struct _DDR_CHANNEL_INFOR_V2 {
  UINT8    DimmType;
  UINT8    DataWidth;
  UINT8    MirrorType;
  UINT8    EccType;
  UINT8    DramType;
  UINT8    RankNum;
  UINT8    RowNum;
  UINT8    ColumnNum;
  UINT8    BankGroupNum;
  UINT8    BankNum;
  UINT16   ModuleManId;
  UINT16   TAAmin;
  UINT16   TRCDmin;
  UINT16   TRPmin;
  UINT16   TRASmin;
  UINT16   TRCmin;
  UINT16   TFAWmin;
  UINT16   TRRDSmin;
  UINT16   TRRDLmin;
  UINT16   TCCDLmin;
  UINT16   TWRmin;
  UINT16   TWTRSmin;
  UINT16   TWTRLmin;
  UINT32   TRFC1min;
  UINT32   TRFC2min;
  UINT32   TRFC4RFCsbmin;
  UINT8    Reserved[32];
} DDR_CHANNEL_INFOR_V2;

//
// DDR Parameter V2
//
typedef struct _PARAMETER_DDR_CONFIG_V2 {
  PARAMETER_HEADER                  Head;
  UINT8                             BitMap;
  UINT8                             Reserved0;
  DDR_MCU_BASE_CONFIG_V2            BaseConfig;
  DDR_TRAINING_DEBUG                Debug;
  UINT8                             Recover;
  UINT8                             SpecifyDramType;
  UINT8                             TrainParam[6];
  UINT8                             Reserved1[7];
  DDR_BYTE_SWAP                     DataSwap;
  DDR_SLICE_DQ_SWIZZLE              DqSwizzle[8];
  UINT8                             Reserved2[12];
  DDR_CHANNEL_INFOR_V2              ChannelInfo;
} PARAMETER_DDR_CONFIG_V2;

//
//DDR Config Parameter V3 Ps2364
//

//
//DDR RAS Config V3
//
typedef struct _DDR_RAS_CONFIG_V3 {
  union {
    struct {
      UINT16    Enable        :    1;
      UINT16    Reserved      :   15;
    } Bits;
    UINT16    Uint16;
  } RasEnable;
  UINT16    Value;
} DDR_RAS_CONFIG_V3;
//
//DDR MCU Base Config V3
//
typedef union _DDR_MCU_BASE_CONFIG_V3 {
  struct {
    UINT64    SpdForce        :    1;
    UINT64    EccEnable       :    1;
    UINT64    DMEnable        :    1;
    UINT64    Performance     :    1;
    UINT64    Preamble2T      :    1;
    UINT64    OneTwo          :    1;
    UINT64    SkipMemClean    :    1;
    UINT64    PdaInvert       :    1;
    UINT64    DqoeTiming      :    2;
    UINT64    MultiRankPer    :    1;
    UINT64    Rervserd0       :    1;
    UINT64    AutoLowPower    :    1;
    UINT64    HalfBitWidth    :    1;
    UINT64    Dbi             :    1;
    UINT64    RefreshMode     :    2;
    UINT64    TempRefresh     :    2;
    UINT64    Crc             :    1;
    UINT64    CaParity        :    1;
    UINT64    Ddr5Ecs         :    1;
    UINT64    Reserved        :    42;
  } Bits;
  UINT64    Uint64;
} DDR_MCU_BASE_CONFIG_V3;

//
//DDR MCU Base Config V3_1
//
typedef union _DDR_MCU_BASE_CONFIG_V3_1 {
  struct {
    UINT64    DdrType         :    1;
    UINT64    SpdBusType      :    1;
    UINT64    Reserved        :    62;
  } Bits;
  UINT64    Uint64;
} DDR_MCU_BASE_CONFIG_V3_1;

//
//All channel ddr information V3
//
typedef struct _DDR_CHANNEL_INFOR_V3 {
  UINT8    DimmType;
  UINT8    DataWidth;
  UINT8    MirrorType;
  UINT8    EccType;
  UINT8    DramType;
  UINT8    RankNum;
  UINT8    RowNum;
  UINT8    ColumnNum;
  UINT8    BankGroupNum;
  UINT8    BankNum;
  UINT16   ModuleManId;
  UINT16   TAAmin;
  UINT16   TRCDmin;
  UINT16   TRPmin;
  UINT16   TRASmin;
  UINT16   TRCmin;
  UINT16   TFAWmin;
  UINT16   TRRDSmin;
  UINT16   TRRDLmin;
  UINT16   TCCDLmin;
  UINT16   TWRmin;
  UINT16   TWTRSmin;
  UINT16   TWTRLmin;
  UINT32   TRFC1min;
  UINT32   TRFC2min;
  UINT32   TRFC4RFCsbmin;
  UINT8    Reserved[32];
} DDR_CHANNEL_INFOR_V3;

//
//DDR Parameter V3
//
typedef struct _PARAMETER_DDR_CONFIG_V3 {
  PARAMETER_HEADER                  Head;
  UINT64                            ChEnableMap;
  DDR_MCU_BASE_CONFIG_V3            McuConfig;
  DDR_MCU_BASE_CONFIG_V3_1          McuConfig1;
  DDR_TRAINING_DEBUG                DebugInfo;
  UINT8                             TrainingRecover;
  UINT8                             DramType;
  UINT8                             TrainingPar[6];
  UINT8                             Resersved1[7];
  DDR_BYTE_SWAP                     Swap;
  DDR_SLICE_DQ_SWIZZLE              SliceDqSwizzle[8];
  UINT32                            Reserved2;
  DDR_CHANNEL_INFOR_V3              ChannelInfo;
  DDR_RAS_CONFIG_V3                 RasConfig;
} PARAMETER_DDR_CONFIG_V3;

//
//DDR Secure base config
//
typedef union _DDR_SECURE_BASE_CONFIG {
  struct {
    UINT8  TzcEnable  :  1;
    UINT8  ZesEnable  :  1;
  } Bits;
  UINT8  Uint8;
} DDR_SECURE_BASE_CONFIG;

//
//struct _DDR_TZC_REGION
//
typedef struct _DDR_TZC_REGION {
  UINT64  StartAddress;
  UINT64  EndAddress;
} DDR_TZC_REGION;

//
//DDR Secure Config
//
typedef struct _DDR_SECURE_CONFIG {
  DDR_SECURE_BASE_CONFIG  BaseConfig;
  DDR_TZC_REGION          TzcAddress[4];
} DDR_SECURE_CONFIG;

//
// C2C Config Ps2364
//
//
// C2C Enable in Die
//
typedef union _C2C_ENABLE_IN_DIE {
  struct {
    UINT32    Die0C2C    :  4;
    UINT32    Die1C2C    :  4;
    UINT32    Die2C2C    :  4;
    UINT32    Die3C2C    :  4;
    UINT32    Die4C2C    :  4;
    UINT32    Die5C2C    :  4;
    UINT32    Die6C2C    :  4;
    UINT32    Die7C2C    :  4;
  } Bits;
  UINT32  Uint32;
} C2C_ENABLE_IN_DIE;

typedef union _C2C_SPEED_IN_DIE {
  struct {
    UINT32    C2C0Speed    :  4;
    UINT32    C2C1Speed    :  4;
    UINT32    C2C2Speed    :  4;
    UINT32    C2C3Speed    :  4;
    UINT32    Reserved     : 16;
  } Bits;
  UINT32    Uint32;
} C2C_SPEED_IN_DIE;

//
//C2C config in Die
//
typedef struct _C2C_CONFIG_IN_DIE {
  PCIE_RAS_CONFIG_V3    RasConfig;
  C2C_SPEED_IN_DIE      Speed;
  UINT32                EqualValue[4];
} C2C_CONFIG_IN_DIE;

typedef struct _PARAMETER_C2C_CONFIG {
  PARAMETER_HEADER       Head;
  C2C_ENABLE_IN_DIE      C2CEnable;
  UINT32                 Reserved0[3];
  C2C_CONFIG_IN_DIE      C2CConfig[8];
} PARAMETER_C2C_CONFIG;

typedef struct _POWER_IC {
  UINT8   Enable;
  UINT8   SlaveAddr;
  UINT8   Reserved[2];
  UINT32  Mode;
  UINT32  Vlsb;
  UINT32  Ilsb;
  UINT32  Plsb;
} POWER_IC;

typedef struct _PARAMETER_BOARD_CONFIG_V2 {
  PARAMETER_HEADER  Head;
  UINT8             BmcEnable;
  UINT8             Reserved[3];
  POWER_IC          PowerIc[8];
} PARAMETER_BOARD_CONFIG_V2;

#pragma pack ()

/**
  Get Parameter information.

  @param[in]      Id        Parameter tabe identifier.
                            PM_PLL_V1      PLL V1 for Pd2008/Ps2364.
                            PM_PLL_V2      PLL V2 for Pe2204.
                            PM_PCIE_V1     PCIE V1 for Pd2008.
                            PM_PCIE_V2     PCIE V2 for Pe2204.
                            PM_COMMON_V1   Common V1 for Pd2008/Pe2204.
                            PM_DDR_V1      DDR V1 for Pd2008.
                            PM_DDR_V2      DDR V2 for Pe2204.
                            PM_DDR_V3      DDR V3 for Ps2364.
                            PM_BOARD       Board.
                            PM_COMMON_V2   Common V2 for Ps2364.
                            PM_C2C         C2C for Ps2364.
                            Other          Invalid ID.
  @param[in,out]  Data      Pointer to paramter information.
  @param[in]      DataSize  Data size to get.

  @retval  EFI_SUCCESS    Get information suceess
  @retval  EFI_NOT_FOUND  Get fail
  @retval  EFI_BUFFER_TOO_SMALL   Buffer size is to small.
  @retval  EFI_INVALID_PARAMETER  Data is NULL, DataSize is 0.

**/
EFI_STATUS
GetParameterInfo (
  IN     UINT32 Id,
  IN OUT UINT8 *Data,
  IN     UINT32 DataSize
  );

/**
  Get Peie V3 information.

  @param[in]      Id        Parameter tabe identifier.
  @param[in]      DieNum    Number of die to get.
  @param[in,out]  Data      Pointer to paramter information.
  @param[in]      DataSize  Data size to get.

  @retval  EFI_SUCCESS            Get information suceess.
  @retval  EFI_INVALID_PARAMETER  Data is NULL, DataSize is 0, or ID is not
                                  PARAMETER_PCIE_MAGIC_V3
  @retval  EFI_NOT_FOUND          Get fail.
  @retval  EFI_BUFFER_TOO_SMALL   Buffer size is to small.
**/
EFI_STATUS
GetParameterPcieV3 (
  IN     UINT32 Id,
  IN     UINT8  DieNum,
  IN OUT UINT8 *Data,
  IN     UINT32 DataSize
  );

/**
  Get Secure Parameter information.

  @param[in]      Id    parameter tabe identifier
  @param[in,out]  Data  pointer to paramter information.
  @param[in]      Size  Size of data to get.

  @retval  EFI_SUCCESS            Get information suceess
  @retval  EFI_INVALID_PARAMETER  Get fail.

**/
EFI_STATUS
GetParameterSecureInfo (
  IN     UINT32 Id,
  IN OUT UINT8  *Data,
  IN     UINT32 Size
  );

/**
  Get die number only for Ps2364.

  @param[out]  Num    Die num.

  @retval      EFI_SUCCESS    Success.
  @retval      Other          Failed.
**/
EFI_STATUS
GetDieNumFromParTable (
  OUT UINT8  *Num
  );


/**
  Print C2C parameter information, only for Ps2364.

  @param[in]  Id      Parameter ID. PM_C2C.
  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintC2CParameter (
  IN  UINT32  Id,
  IN  VOID    *Buffer
  );

/**
  Print PLL parameter information.

  @param[in]  Id      Parameter ID. PM_PLL_V1 for Pd2008/Ps2364,
                      PM_PLL_V2 for Pe2204.
  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintPllParameter (
  IN  UINT32  Id,
  IN  VOID    *Buffer
  );

/**
  Print COMMON parameter information.

  @param[in]  Id      Parameter ID.
                      PM_COMMON_V1 for Pd2008/Pe2204.
                      PM_COMMON_V2 for Ps2364
  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintCommonParameter (
  IN  UINT32  Id,
  IN  VOID    *Buffer
  );

/**
  Print PCIE parameter information.

  @param[in]  Id      Parameter ID.
                      PM_PCIE_V1 for Pd2008.
                      PM_PCIE_V2 for Pe2204.
                      PM_PCIE_V3 for Ps2364.
  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintPcieParameter (
  IN  UINT32  Id,
  IN  VOID    *Buffer
  );

/**
  Print DDR parameter information.

  @param[in]  Id      Parameter ID.
                      PM_DDR_V1 for Pd2008.
                      PM_DDR_V2 for Pe2204.
                      PM_DDR_V3 for Ps2364.
  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintDdrParameter (
  IN UINT32  Id,
  IN VOID    *Buffer
  );

/**
  Print board parameter information.

  @param[in]  Id      Parameter ID.
                      PM_BOARD_V2 for Ps2364.

  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintBoardParameter (
  IN UINT32  Id,
  IN VOID    *Buffer
  );

#endif  /* PARAMETER_H_ */
